High Density PCB Layout |
3D Viewing and Verification |
| Designing with the latest FPGA and BGA based packages requires complex multilayer routing and track length tuning. Design rules are configured for tracking / layer use and specific track length matching. Validating the design through Altiums extensive design rule checker mean prototypes with less errors. | The ability to review the board design and component positions in a rendered 3D image reduces layout errors. Footprints designed to IPC standards and 3D components created from manufacturers physical package dimensions permit 100% validation. |
| PCB Designer with High Speed digital knowldege? PCB Designer with EMC knowledge. PCB Designer with FPGA experience. PCB Designer with software skills. Use Microdex! | |
Altium Designer |
Altium Designer Tips |
PCB Designer Tip #1 |
Routing a bus with matched length? Use the PCB panel a select the bus class and sort the nets by length. The first net to route is the one with the largest manhatten length. This then becomes your overall target matching length. |
PCB Designer Tip #2 |
For better EMC grounding scheme considering defining net ties to make your GND star points. |
PCB Designer Tip #3 |
If you need to match track lengths for a whole bus including strobe / control signals, use a harness on the schematic, this will create a complete net class of the group. |
Licensed Tools |
Altium designer 6 |